Integrated circuit devices are typically tested after fabrication to ensure device performance according to functional specifications. Typically, an automatic electrical test system is programmed to provide an integrated circuit device with a simulated operating environment. Very-large-scale-integration (VLSI) devices require an automatic electrical test system capable of processing a large number of high-speed input/output pins.
In a typical automatic electrical test system, an interface between a timing generator and the driving pin electronics of the system must accommodate the data rate of the device under test (DUT). High DUT data rates necessitate high IO bandwidth between the timing generator and the driving pin electronics, which can be very costly to implement. To reduce the IO bandwidth between the timing generator and the driving pin electronics, while accommodating the high DUT data rate, typically two channels, each having half the required data rate, are XORed together.
For testing, circuitry in the electrical test system applies a test pattern utilizing XOR data formatting to the DUT and receives outputs from the DUT in response to the test patterns. Typically, the entire pattern is compiled and loaded onto the Deep Pattern Memory (DPM) of the tester to be executed by the tester and converted from a representation of driven ONEs and ZEROs to a representation which drives a change from one signal state of the DUT to another signal state. A change from one signal state to another is called a transition. Because a state in the pattern depends on the previous state, typically any change to the pattern ripples through the entire pattern sequence. To avoid the ripples, a corrected pattern from the location of the change to the end of the pattern must be recompiled and loaded. This is prohibitively time consuming for all but short patterns.
Additionally, complete patterns are concatenated from many short pattern segments. Pattern segments can be reused and will behave differently depending on whether the entry state to the segment is a ONE or a ZERO.